For a bolometer array, a dominant factor that limits the sensitivity and dynamic range of the bolometer array, such as might be used for thermal imaging, is the offset current (or voltage) that is present even in the absence of a signal. That is, current flows through a resistor regardless of whether there is an infrared signal present, and that current is very large compared to the small differential currents that result from exposure to typical infrared signals. Readout electronics typically integrate the current that flows through each bolometer element, thereby converting the current to a voltage. Every electronic circuit has limitations on the size of voltage it can handle, and because of these voltage size limitations, the offset current effectively limits the voltage range available for signal.
Most of the offset current can be removed by adding another resistor of approximately equal value in series with each bolometer resistor, and then setting the voltages at the bias and ground nodes such that the node between the two resistors (the signal node) is at an appropriate intermediate value. The voltage at the signal node can then swing up or down accordingly as the bolometer resistance decreases or increases. However, the addition of a resistor adds noise, and there is often insufficient space in the pixel unit cell to add a resistor. Furthermore, if a resistor were added it would have to be fabricated in a different process than the bolometer resistors, because they occur on different levels of the integrated circuit structure. This would add to the difficulty in matching resistor values as well as values of their temperature coefficients of resistance, and it would complicate the fabrication process.
U.S. Pat. No. 5,128,534 provides one solution to this problem by adding a ramp current to the backside of a capacitor within the pixel read-out circuitry that acts to subtract charge from the integration capacitor. U.S. Pat. No. 7,268,607 provides another solution having a subtraction of a fixed charge. U.S. Pat. Nos. 5,128,534 and 7,268,607 are hereby each incorporated by reference in its entirety.
FIG. 1 (Prior Art) is a circuit diagram of an embodiment 100 for a read-out cell including current subtraction that relates to U.S. Pat. No. 5,128,534. A bias voltage Vdet is applied to the common node of the bolometer resistor (Rdet) 102, and a voltage Vgg is applied to the gate of a MOSFET (metal oxide semiconductor field effect transistor) 104 operating in saturation. The bias voltage across the resistor is Vdet−(Vgg+VT), where VT is the bias transistor threshold voltage. To end an integration cycle, the switch 106 is closed, thereby grounding node 107. To begin the next cycle, the switch 106 is opened, thereby allowing charge to build up on Vint node 107 and to be stored on integration capacitor (Cint) 108. Essentially simultaneously with the opening of the switch, the ramp voltage (Vramp) 110 is set to V0 from which point it ramps linearly downward toward ground (0 volts).
While these prior solutions improve bolometer array sensitivity, further improved solutions are still needed to better improve the sensitivity of infrared bolometer arrays.